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NXP Semiconductors /QN908XC /BLEDP /DP_TOP_SYSTEM_CTRL

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Interpret as DP_TOP_SYSTEM_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RX_PDU_LEN_IN0 (AA_SEL)AA_SEL 0 (PDU_LEN_SEL)PDU_LEN_SEL 0H_IDX0 (RX_EN_SEL)RX_EN_SEL 0 (TX_EN_SEL)TX_EN_SEL 0 (RX_REQ)RX_REQ 0 (TX_REQ)TX_REQ 0RX_MODE 0 (ANT_DATA_START)ANT_DATA_START 0 (DET_MODE)DET_MODE

Description

datapath system control register

Fields

RX_PDU_LEN_IN

pdu length user programmed header+payload unit is bit.
AA_SEL

access address selection
PDU_LEN_SEL

pdu length selection
H_IDX

h index from 0.25 to 0.75 default is 0.5.
RX_EN_SEL

rx enable select signal
TX_EN_SEL

tx enable select signal
RX_REQ

rx request.
TX_REQ

tx request.
RX_MODE

rx mode
ANT_DATA_START

ant mode data start signal need write 0 first then to 1.
DET_MODE

detection mode 0low ppwer mode 1high performance mode.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data